| Type | Instance | Vendor | Component | |
|---|---|---|---|---|
| Processor | cpu | xilinx.ovpworld.org | microblaze | |
| Peripheral | gpio | xilinx.ovpworld.org | axi-gpio | |
| Peripheral | node | safepower.ovpworld.org | NostrumNode | |
| Memory | ramS | ovpworld.org | ram | |
| Bus | pBus | (builtin) | address width:32 | |
| Bus | gpiodprBus | (builtin) | address width:32 | |
| Bridge | gpiodprBridge | (builtin) |
Information for Zynq_PL_NostrumNoC_node
This page provides detailed information about the safepower.ovpworld.org Zynq_PL_NostrumNoC_node Virtual Platform / Virtual Prototype.
Licensing
Open Source Apache 2.0
Description
This module implements a NoC node used to implement an example NoC in the Xilinx Zynq Programmable Logic (PL).
This PL configuration instances one Xilinx MicroBlaze processor with a local memory and a NoC interface peripheral.
Limitations
This is baremetal only.
Reference
No Reference
Location
The Zynq_PL_NostrumNoC_node virtual platform is located in an Imperas/OVP installation at the VLNV: safepower.ovpworld.org / module / Zynq_PL_NostrumNoC_node / 1.0.
Platform Summary
Table 1: Components in platform
Platform Simulation Attributes
Table 2: Platform Simulation Attributes
| Attribute | Value | Description |
|---|---|---|
| stoponctrlc | stoponctrlc | Stop on control-C |
External Ports for Module Zynq_PL_NostrumNoC_node
Table 3: External Ports
| Port Type | Port Name | Internal Connection |
|---|---|---|
| busport | gpiodprPort | gpiodprBus |
| netport | syncInPort | syncIn |
| netport | syncOutPort | syncOut |
| netport | gpio_outP | gpio_out |
| netport | gpio2_outP | gpio2_out |
| netport | gpio_inP | gpio_in |
| netport | gpio2_inP | gpio2_in |
| packetnetport | networkNodePort | networkNode |
Processor [xilinx.ovpworld.org/processor/microblaze/1.0] instance: cpu
Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:
Table 4: Processor Instance 'cpu' Parameters (Configurations)
| Parameter | Value | Description |
|---|---|---|
| mips | 100 | The nominal MIPS for the processor |
Memory Map for processor 'cpu' bus: 'pBus'
Processor instance 'cpu' is connected to bus 'pBus' using master port 'INSTRUCTION'.
Processor instance 'cpu' is connected to bus 'pBus' using master port 'DATA'.
Table 5: Memory Map ( 'cpu' / 'pBus' [width: 32] )
| Lo Address | Hi Address | Instance | Component |
|---|---|---|---|
| 0x0 | 0x3FFFFFF | ramS | ram |
| 0x40000000 | 0x400001FF | gpio | axi-gpio |
| 0x41000000 | 0x410001FF | gpiodprBridge | bridge |
| 0x70020000 | 0x7003FFFF | node | NostrumNode |
Table 6: Bridged Memory Map ( 'cpu' / 'gpiodprBridge' / 'gpiodprBus' [width: 32] )
| Lo Address | Hi Address | Instance | Component |
|---|
Net Connections to processor: 'cpu'
There are no nets connected to this processor.
Peripheral Instances
Peripheral [xilinx.ovpworld.org/peripheral/axi-gpio/1.0] instance: gpio
Description
Xilinx AXI General Purpose IO
Licensing
Open Source Apache 2.0
Limitations
This model implements the AXI GPIO
Reference
pg144-axi-gpio Vivado Design Suite October 5, 2016
There are no configuration options set for this peripheral instance.
Peripheral [safepower.ovpworld.org/peripheral/NostrumNode/1.0] instance: node
Description
The Nostrum Network on Chip (NoC) node peripheral for SafePower Project
Licensing
Open Source Apache 2.0
Limitations
This model implements the Nostrum NoC node processor interface. It does not model any timing in the transfer of messages between nodes.
Reference
Generated using the VHDL file generic_interface_to_noc_static.vhd provided as part of example December release.
Table 7: Configuration options (attributes) set for instance 'node'
| Attributes | Value |
|---|---|
| id | nocid |
| generateSync | |
| sendChannelSize | |
| mboxSize |
Information on the Zynq_PL_NostrumNoC_node Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library
http://www.ovpworld.org: VMI Morph Time (VMI MT) API Reference Guide
http://www.ovpworld.org: Using OVP Fast Processor Models with OVPsim and other simulators
http://www.ovpworld.org: riscvOVPsim. A complete RISC-V ISS for bare-metal software development and Specification Compliance Test Development
http://www.ovpworld.org: RISC-V Bare Metal Demos Video Presentation
Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes for Embedded Software Development and Test Automation.