Information for Or1kUclinux

This page provides detailed information about the imperas.ovpworld.org Or1kUclinux Virtual Platform / Virtual Prototype.

Description
Platform for an Or1k Processor to execute uCLinux.

Licensing
Open Source Apache 2.0

Limitations
Provides sufficient functionality to execute uCLinux operating system and OR1K elf files

Location
The Or1kUclinux virtual platform is located in an Imperas/OVP installation at the VLNV: imperas.ovpworld.org / platform / Or1kUclinux / 1.0.

Platform Summary

Table 1: Components in platform

Platform Simulation Attributes

Table 2: Platform Simulation Attributes

---

Command Line Control of the Platform

Built-in Arguments

Table 3: Platform Built-in Arguments

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.

---

Processor [ovpworld.org/processor/or1k/1.0] instance: cpu1

Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:

Table 4: Processor Instance 'cpu1' Parameters (Configurations)

Memory Map for processor 'cpu1' bus: 'bus1'
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.

Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.

Table 5: Memory Map ( 'cpu1' / 'bus1' [width: 32] )

Net Connections to processor: 'cpu1'

Table 6: Processor Net Connections ( 'cpu1' )

---

Peripheral Instances

---

Peripheral [national.ovpworld.org/peripheral/16550/1.0] instance: uart1

Limitations
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
Values written to the MCR are ignored. Loopback mode is not supported.

Description
Interrupts and FIFOs are supported.
Registers are aligned on 1 byte boundaries.

Limitations
Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.

Description
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.

Licensing
Open Source Apache 2.0

Description
16550 UART model

Reference
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)

Table 7: Configuration options (attributes) set for instance 'uart1'

---

Other Sites/Pages with similar information

Information on the Or1kUclinux Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library

A couple of documents (from other related sites that might be of interest)
http://www.ovpworld.org: VMI Operating System support (VMI OS) API Reference Guide
http://www.ovpworld.org: iGen Peripheral Generator User Guide

Two Videos on these models (from other sites)
http://www.ovpworld.org: MIPS Demo Video Presentation
http://www.ovpworld.org: RISC-V Bare Metal Demos Video Presentation

---

Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes for Embedded Software Development and Test Automation.