Type | Instance | Vendor | Component | |
---|---|---|---|---|
Processor | cpu0 | mips.ovpworld.org | mips32_r1r5 | 4Km |
Processor | cpu1 | mips.ovpworld.org | mips32_r1r5 | 4Km |
Memory | memory0 | ovpworld.org | ram | |
Memory | memory1 | ovpworld.org | ram | |
Bus | bus0 | (builtin) | address width:32 | |
Bus | bus1 | (builtin) | address width:32 |
Information for BareMetalMips32Dual
This page provides detailed information about the mips.ovpworld.org BareMetalMips32Dual Virtual Platform / Virtual Prototype. Table 1: Components in platform
Description
Bare Metal Platform for a MIPS32 Processor (default 4Km).
The bare metal platform instantiates two MIPS32 processor instances.
The processor operates using big endian data ordering.
It creates contiguous memory from 0x00000000 to 0xFFFFFFFF.
The platform can be passed any application compiled to a MIPS elf format. The
same application executes on each processor. There is no sharing of data.
It may also be passed a new variant to be used (default 4Km)
./platform.OS.exe --program application.CROSS.elf [--variant
Licensing
Open Source Apache 2.0
Limitations
BareMetal platform for execution of MIPS MIPS32 binary files compiled with CodeSourcery CrossCompiler toolchain.
Location
The BareMetalMips32Dual virtual platform is located in an Imperas/OVP installation at the VLNV: mips.ovpworld.org / platform / BareMetalMips32Dual / 1.0.
Platform Summary
Platform Simulation Attributes
Table 2: Platform Simulation Attributes
Attribute | Value | Description |
---|---|---|
stoponctrlc | stoponctrlc | Stop on control-C |
Command Line Control of the Platform
Built-in Arguments
Table 3: Platform Built-in Arguments
Attribute | Value | Description |
---|---|---|
allargs | allargs | The Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products |
For example: myplatform.exe -help
Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf
Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.
Processor [mips.ovpworld.org/processor/mips32_r1r5/1.0] instance: cpu0
Processor model type: 'mips32_r1r5' variant '4Km' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/mips.ovpworld.org/processor/mips32_r1r5/1.0/doc
- the OVP website: OVP_Model_Specific_Information_mips32_r1r5_4Km.pdf
Description
MIPS32 Configurable Processor Model
Licensing
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations
If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
Verification
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features
only MIPS32 Instruction set implemented
MMU Type: Fixed Mapping
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu0' it has been instanced with the following parameters:
Table 4: Processor Instance 'cpu0' Parameters (Configurations)
Parameter | Value | Description |
---|---|---|
endian | big | Select processor endian (big or little) |
mips | 100 | The nominal MIPS for the processor |
semihostvendor | mips.ovpworld.org | The VLNV vendor name of a Semihost library |
semihostname | mips32Newlib | The VLNV name of a Semihost library |
Table 5: Processor Instance 'cpu0' Parameters (Attributes)
Parameter Name | Value | Type |
---|---|---|
variant | 4Km | enum |
Memory Map for processor 'cpu0' bus: 'bus0'
Processor instance 'cpu0' is connected to bus 'bus0' using master port 'INSTRUCTION'.
Processor instance 'cpu0' is connected to bus 'bus0' using master port 'DATA'.
Table 6: Memory Map ( 'cpu0' / 'bus0' [width: 32] )
Lo Address | Hi Address | Instance | Component |
---|---|---|---|
0x0 | 0xFFFFFFFF | memory0 | ram |
Net Connections to processor: 'cpu0'
There are no nets connected to this processor.
Processor [mips.ovpworld.org/processor/mips32_r1r5/1.0] instance: cpu1
Processor model type: 'mips32_r1r5' variant '4Km' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/mips.ovpworld.org/processor/mips32_r1r5/1.0/doc
- the OVP website: OVP_Model_Specific_Information_mips32_r1r5_4Km.pdf
Description
MIPS32 Configurable Processor Model
Licensing
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations
If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
Verification
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features
only MIPS32 Instruction set implemented
MMU Type: Fixed Mapping
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:
Table 7: Processor Instance 'cpu1' Parameters (Configurations)
Parameter | Value | Description |
---|---|---|
endian | big | Select processor endian (big or little) |
mips | 100 | The nominal MIPS for the processor |
semihostvendor | mips.ovpworld.org | The VLNV vendor name of a Semihost library |
semihostname | mips32Newlib | The VLNV name of a Semihost library |
Table 8: Processor Instance 'cpu1' Parameters (Attributes)
Parameter Name | Value | Type |
---|---|---|
variant | 4Km | enum |
Memory Map for processor 'cpu1' bus: 'bus1'
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.
Table 9: Memory Map ( 'cpu1' / 'bus1' [width: 32] )
Lo Address | Hi Address | Instance | Component |
---|---|---|---|
0x0 | 0xFFFFFFFF | memory1 | ram |
Net Connections to processor: 'cpu1'
There are no nets connected to this processor.
Information on the BareMetalMips32Dual Virtual Platform can also be found on other web sites :
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryPlatform
www.imperas.com has more information on the model library
http://www.ovpworld.org: VMI Memory Modeled Component (VMI MMC) API Reference Guide
http://www.ovpworld.org: Visualization used in Virtual Platforms.
http://www.ovpworld.org: Renesas v850 Bare Metal Video Presentation
http://www.ovpworld.org: OR1K Demo Video Presentation
Currently available Imperas / OVP Virtual Platforms / Virtual Prototypes for Embedded Software Development and Test Automation.